Digital System Design Using Verilog HDL for FPGA Implementation
13 - 16 JUNE 2023
MS TEAMS
9.00AM - 1.00PM
RM 1,800 FOR PROFESSIONALS
10% Discount for Early Bird (until 13 May 2023) / Group / Students
INTRODUCTION
Hardware Description Languages can be used for both design implementation and design simulation. It is important to understand that certain HDL constructs that can be used to simulate a design may not be translated into physical hardware. The designer must be aware of the specific constructs that may be used to generate desired hardware. A very important thing to remember when you are writing HDL code is that you are describing real hardware, not writing a computer program.
This course which requires the participant to purchase his or her own FPGA board explores the development of FPGA-based digital systems using one of the most popular hardware description languages, namely Verilog. The course offers a deep foundation in FPGA principles, practices, and applications and provides an overview of more complex topics in research domain. Important concepts are demonstrated by using real-world examples and synthesizable codes for inexpensive FPGA platforms such as Arty-7 boards.
It will familiarize the audience with the basics of digital design, FPGA architecture, block RAM, FPGA clock management, and Verilog HDL. The following book is recommended for post-course reference: Digital System Design with FPGA: Implementation Using Verilog and VHDL, 1st Edition by Cem Unsalan and Bora Tar.
Field Programmable Gate Array (FPGA)
Demonstration of Arty Artix-7 FPGA Boards
The Vivado Design Suite
Introduction to Verilog HDL
Data Types and Operators
Combinational Circuit Blocks
Data Storage Elements
Sequential Circuits
OBJECTIVES
Upon completion of this course, participants will be able to:
WHO SHOULD ATTEND?
1. Digital System Designing using Verilog HDL
2. Prototyping of digital systems using FPGAs
3. Pre-silicon ASIC validation using FPGAs
4. Building career in FPGA/ASIC design
1. Associate Professor Dr. Mohd Zuki Yusoff (UTP)
Dr Mohd Zuki Yusoff specializes in embedded systems (microprocessor and microcontroller) teaching/training. He is currently an associate professor at UTP and is the Head of Centre for Intelligent Signal and Imaging Research (CISIR) and a member of the Institute of Health & Analytics (IHA). He is currently undertaking research in brain signal processing (brain computer interface; learning effectiveness; driver drowsiness; road rage). He holds one patent related to the extraction of event related potentials from background EEG, and two more patents in telecommunications related areas. He is a member of the following learned societies and professional body: IEEE, Tau Beta Pi—the National Engineering Honorary Society, Eta Kappa Nu—the Electrical and Computer Engineering Honorary Society. Dr. Zuki has accumulated over 30 years of experience working with various industries and academic/training institutions; these include Universiti Teknologi PETRONAS (UTP), Celcom Academy, Politeknik Sultan Abdul Halim Mu’adzam Shah (POLIMAS), Malaysian Institute of Microelectronic Systems (MIMOS), and Singatronics (M) Sdn Bhd. He is a certified Curriculum Designer & Developer, awarded by Sepang Institute of Technology (SIT) and Douglas Mawson Institute of TAFE in March 1999.
2. Muhammad Sajjad (UTP)
*fee quoted does not include SST, GST, HRDF service fee / VAT or withholding tax (if applicable).
*fee quoted does not include SST, GST, HRDF service fee / VAT or withholding tax (if applicable).
Centre for Advanced & Professional Education (CAPE)
Level 8, Permata Sapura, Kuala Lumpur City Centre, 50088 Kuala Lumpur
+605 - 368 7558 /
+605 - 368 8485
cape@utp.edu.my